Solid state linear photosensor

ABSTRACT

There is disclosed a linear solid-state photosensor which exhibits avalanche multiplication and which has a resolution capability comparable to that of silver halide photography. The photosensor is of the type which is suitable for use in a slit image camera of the type commonly carried by airplanes, satellites, or any other moving vehicle which can position the image forming slit so that the scene to be photographed passes by it. In this event, of course, the movement of the scene relative to the camera replaces the more conventional movement of the film relative to the camera&#39;&#39;s optical axis. The photosensor of this invention replaces the film of the camera in such applications and is capable of providing a direct conversion of the light image to electrical signal output in a manner analogous to that of a television camera. There is also disclosed herein a method of manufacturing the linear solid-state photosensor so as to achieve the desired resolution.

' United States Patent [72] inventor Murray Bloom Los Angeles,Calii. [211 Appl. No. 746,072 [22] Filed July 19, 1968 [45] Patented Sept. 28,1971 [73] Assignee TRW Inc.

Redondo Beach, Calif.

[54] SOLID STATE LINEAR PHOTOSENSOR Attorneys-Daniel T. Anderson, AlfonsValukonis and Harry 1. Jacobs ABSTRACT: There is disclosed a linearsolid-state photosensor which exhibits avalanche multiplication andwhich has a resolution capability comparable to that of silver halidephotography. The photosensor is of the type which is suitable for use ina slit image camera of the type commonly carried by airplanes,satellites, or any other moving vehicle which can position the imageforming slit so that the scene to be photographed passes by it. In thisevent, of course, the movement of the scene relative to the camerareplaces the more conventional movement of the film relative to thecamera's optical axis. The photosensor of this invention replaces thefilm of the camera in such applications and is capable of providing adirect conversion of the light image to electrical signal output in amanner analogous to that of a television camera. There is also disclosedherein a method of manufacturing the linear solid-state photosensor soas to achieve the desired resolution.

EFFECTIVE LENGTH OF CAPACITOR PATENTED SEP28 1971 3509-375 sum 1 [1F 3 HR a H x l Murray Bloom RI INVENTOR.

l4 l BY WZM ATTORNEY PATENTz-ln SEP28 1911 609.375

sum 2 OF 3 I Eoui Ei n EFFECTIVE LENGTH OF CAPAClTOR Murray Bloom F i g8 INVENTOR.

e @MZW ATTORNEY PATENTEU SEP28 197i 3 6 O9 3 7 5 saw 3 BF 3 EFFECTIVELENGTH OF CAPACITOR J D C 52 4 Murray Bloom INVENTOR.

ZWZW ATTORNEY SOLID STATE LINEAR PHOTOSENSOR CROSS-REFERENCE TO RELATEDAPPLICATION The present invention is an application of an improvementover the method of sputter fabrication of silicon semiconduc torrectifying junctions disclosed in British Pat. No. 1,077,320 publishedJuly 26, 1967 which in turn was based upon U.S. application Ser. No.449,885 filed Apr. 21, 1965 by the inventor herein, and now abandoned.

BACKGROUND OF THE INVENTION Aerial phototelemetry systems depend uponconversion of an optical image formed by a slit-type camera toelectrical signals representative of the relative brightness of eachelement of the image formed by the slit. In practice the elements of theslit image are scanned while the entire apparatus is in motion relativeto the image to be photographed. This motion replaces the motion of thefilm in the conventional motionpicture-type camera or the motionproduced by the vertical sweep in a still television camera. Thus, sincethe camera is in motion and contains only a slit forming a linear image,one needs only to sweep horizontally along a single linear array ofphotosensors. It is, of course, desirable to provide photo sensors whichafford a direct conversion of optical image intensity into electricalsignals varying in intensity or amplitude in proportion to thebrightness of the image without first interposing the conventionalphotographic film.

For this purpose the prior art has made various attempts at fabricatinga solid-state linear photosensor. The problems in such photosensors havebeen to obtain sufficient sensitivity or signal-to-noise ratio whilestill maintaining adequate resolution comparable to that of the silverhalide normally used in the conventional photographic process which itis desired to eliminate as an intermediate step. Presently availabledevices have resolutions far inferior to that of silver halide, or, iftheir resolution is high, they suffer from lack of photosensitivity.

It is thus an object of this invention to provide a linear solidstatephoto sensor which will exhibit avalanche multiplication and will have aresolution comparable to that of silver halide.

' SUMMARY OF THE INVENTION In accordance with the present invention, thesputter deposition technique of the above-noted British Pat. No.1,077,320 is modified by omitting the mask used therein to produceseparate diodes on a single wafer and is further modified by adeliberate reliance on what had heretofore been considered undesirableoxygen and nitrogen impurities to produce a high sheet resistance in thesputter deposited layer which in effect forms a large number of separatediodes insulated from each other by silicon dioxide or silicon nitridelayers. This technique is used in conjunction with other techniques offabricating a monolithic integrated circuit. This integrated circuitcontains a series of so called read diodes each of which is in circuitwith a write diode. The array of write diodes are exposed to the linearimage from the slit and supply current to the read diodes. The readdiodes in turn are connected in circuit to a readout resistor by ascanning means which changes their resistance so that they act as aswitch. This scanning means can typically be any scanning light beamsuch as the beam from a flying spot scanner or a deflected laser beam.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings:

FIG. 1 is a schematic circuit diagram illustrating the principle of theinvention.

FIG. 2 is a schematic circuit diagram similar to FIG. 1 but showing morepractical detail utilizing integrated devices.

FIG. 3 is a cutaway perspective view illustrating the structure of theintegrated device which operates in the manner shown in the circuitdiagrams of FIGS. 2 and 5.

FIG. 8 is a cutaway perspective view of the structure of the device ofthe type illustrated in FIG. 7.

FIG. 9 is a schematic circuit diagram of another embodiment of thedevice.

FIG. 10 is a cutaway perspective view of a device structure embodyingthe circuit of FIG. 9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Consider now the schematiccircuit diagram of FIG. 1. A plurality of write diodes, W W W W W etc.,are connected in parallel to a readout switch the arm of which isconnected by conductor 11 through load resistor 10 to the positive sideof an input voltage source connected between terminals l2 and 13.Terminal 13 is connected to the opposite terminals of the diodes byconductor 14 the circuit connection being such that any diode connectedto the rotary arm RA of a switch is backbiased by the input voltage. Anoutput signal is taken across terminals 15 and 16 on opposite ends ofload resistor 10. The diodes are electrically connected in parallelrelationship to each other and are physically juxtapositioned next toeach other in a linear array. A lens L focuses a slit or linear image onthe diodes intensity of which may vary as between individual diodes.

It is well known that avalanche multiplication in diodes can result inoverall quantum efficiencies greater than one. The value of E is chosento be such that a relatively small amount of current passes through theback-biased diodes W when the are dark. When they are illuminated, theamount of current which they will pass and hence the value of E at theload resistor 10 will depend upon the amount of light falling onwhatever diode has been selected by the rotary arm of the switch R. Theuse of a mechanical switch as shown is obviously impractical if highswitching speeds are needed. Therefore, the circuit may be modified asshown in FIG. 2 so as to replace each switch contact with anotherback-biased diode R. In Fig. 2 parts corresponding to identical parts inFig. I are indicated by the same reference character, as is truethroughout the drawings. However, the newly added diodes are indicatedby an R with the appropriate subscript to correlate the read diode toits corresponding write diode with which it is connected in electricalseries relationship as shown. Thus, read diode R, is connected in serieswith write diode W between conductors l1 and 14. Similarly read diode Ris connected in series with write diode W also between conductors l1 and14. A similar relationship holds for all other diodes.

It will thus be seen that the circuit of FIG. I has been modified asshown in FIG. 2 so as to replace each of the mechanical switch contactswith another back-biased diode of the R series. Each of these R diodesis in turn scanned with an intense spot of light from a scanning sourceS. This scanning source may be a conventional flying spot scanner or anyother suitable deflectable light source. If a flying spot scanner isused the cathode-ray tube may be modified in shape so as to provide arelatively flat configuration affording only a horizontal linear sweepin order to save space. If intensity of light and scanning resolution isof critical importance in a given system optical means for deflecting alaser beam can readily be provided. Since the details of the scanningmechanism per se do not form a part of this invention, the scan sourceis indicated only schematically.

When each of the R diodes is scanned with a spot of light, the normallyback-biased R diodes act as a switch which closes and allows current toflow through the corresponding W diodes. That is to say, the scanningspot falling on the photosensitive diode lowers its resistance so thatthis resistance falls from a fixed high value to a fixed low value.Reducing this resistance which is in series with that of the W diodesallows current to flow through the corresponding series connected Wdiode. This current is, as before, determined in the conducting state ofthe pair by the amount of light falling on the particular W diode and issensed as a voltage across the load resistor 10.

If built with discrete components, the circuit sketched in FIG. 2 wouldnot provide the resolution desired. The resolution desired can beobtained, however, if the circuit is fabricated as an integratedmicrocircuit by making use of the peculiar properties of sputteredsilicon which have initially been discussed in the above-noted Britishpatent. A sputtering method is therein disclosed wherein a silicon bodyis connected to form a cathode in circuit with a metallicanode acrosswhich a controlled power source is connected. The cathode and anode arecoaligned in a vacuum chamber with a semiconductor substrate such as asilicon wafer positioned between them. When the voltage results in aglow discharge, atoms from the silicon cathode are deposited on thesilicon wafer. A detailed analysis of the method is presented in theBritish patent. As described therein, the intention was to form aplurality of separate diodes on the substrate by interposing a nickel orother metallic mask between it and the cathode the mask having apertureswhich permitted deposition only in discrete areas. Starting from thispremise an attempt was made to minimize the oxygen or nitrogen impurityof the argon gas which was used as the reduced pressure atmosphere inthe vacuum vessel. In practice low resistance values can be achieved ifdesired if an appropriate getter is used to reduce the oxygen andnitrogen impurity. In the absence of such a getter, however, the sheetresistance of the sputter deposited material remains relatively high.However, it has now been found that this sheet resistance issufficiently high and sufficiently nonuniform in distribution so that itis preferred to permit the oxygen and/or nitrogen impurities to remainin commercial grade tank argon so that the silicon dioxide and thesilicon nitride formed in the sputtering process will form insulatingdeposits which in effect produces a plurality of discrete diodesseparated only by molecular layers of these insulators. The use of theapertured mask is thus eliminated and increased resolution is obtained.If no getter is used satisfactory results have been obtained by using anatmosphere either of research grade argon which is 99.9995 percent pureor by using commercial grade argon which is 99.995 percent pure. Thus itfollows that the oxygen and nitrogen impurity content in the evacuatedvessel will at a minimum be in the range of from 0.0005 to 0.005 of apercent. Additional oxygen may result from outgassing from the walls ofthe vessel. Otherwise the process of laying down the sputtered layers tobe discussed below is the same as that set forth in the British patent.Of course, once a sputtered layer has been deposited on a silicon wafera linear chip of desired dimensions may be diced from the wafer. It isfound that such a linear chip has very high lateral or sheet resistanceand thus forms in effect a plurality of juxtaposed diodes orjunctions ofthe type discussed individually in the British patent.

From the above it will be seen that one can by sputtering prepare alayer of one conductivity type of silicon upon a substrate of theopposite conductivity type in such a way that the deposited film doesnot conduct parallel to the film plane, but does conduct normal to it.(In all of the diagrams and structurcs herein it will be understood thatall P-regions can be interchanged with all of the N-regions.) Such afilm on a substrate is equivalent to an array of submicroscopic diodes,each of which is dielectrically isolated from its neighbors.

In Fig. 3 there is shown one way of using this material to fabricate theequivalent of the circuit shown in FIG. 2. The structure shown isfabricated on a wafer produced by modifying one produced by thedielectric isolation technique disclosed in U.S. Pat. No. 3,320,485issued to J. L. Buie. It consists of islands of single crystal siliconsuch as the P-type single crystal P and the N-type single crystal Nsurrounded first by a layer of silicon dioxide D adjacent to each singlecrystal and having a matrix of polycrystalline silicon C positionedbetween the silicon dioxide layers. On this wafer there has beendeposited by means of the above described sputtering technique a layer20 of N-type sputtered silicon above the P- type single crystal P and alayer 21 of P-type sputtered silicon above the N-type single crystal N.This sputtered silicon layer is less than one micron thick. That portionover the single crystal strip will form the array of rectifyingjunctions. The two portions are separated by a continuation of thesilicon dioxide insulating barrier D. Over the sputtered layer separatedby the insulating strip D there is deposited a transparent conductivelayer which, by means of conventional photoengraving operations, isformed into strips 0.1 mil wide on 0.2 mil centers. These transparentstrips are indicated by the reference character T in Fig. 3 Thoseisolated diodes which do not happen to be between one of thesetransparent conductive strips and the silicon single crystal strip are,essentially, out of the circuit and need not be considered further.Those that do fall between are connected in parallel with one another bythe conductor T. The line image to be sensed falls on junctions in thestrip 20 by being transmitted through the transparent conductive stripsand penetrating far enough into the layer of sputtered silicon so thatthe hole-electron pairs which are generated can be collected at thejunctions formed between the P-type single crystal P and the sputtereddeposit strip 20. The scanning spot used to switch the R diodessimilarly falls on the strip 21. The R diodes, of course, are formedbetween strip 21 and the single crystal strip N. The equivalent ofconductor 14 in FIG. 2 is provided by a metallization layer 14a in FIG.3 which serves as the writing diode bus bar and the equivalent ofconductor 11 in FIG. 2 is provided in the device of FIG. 3 by ametallization layer which serves as the reading diode bus bar. Of courseit will be understood that the device of Fig. 3 is then electricallyconnected in series with the appropriate external voltages and loadresistor and that means are provided to impress the input image on strip20 and to impress the scanning spot on strip 21.

The resolution of the device shown in FIG. 3 depends only upon the widthand spacing of the transparent conductors T. If widths and spacing of0.1 mil are used, the device can resolve 5,000 lines per inch. Themicroscopic diodes under each individual transparent conductive layerare of course connected in parallel by the conductor once it has beenapplied so that they form effectively a single diode.

Initially the sputtered silicon layer (which is less than one micronthick) forms rectifying junctions over the single crystal strips whereasthe portion which is deposited over the silicon dioxide strip, althoughthey will be in the form of isolated crystallites, will constitute anonconducting layer since they originate at an insulating substrate.

It is to be noted that the structure shown in FIG. 3 is only one of manywhich can be devised. For example, if it is desired not to employ astarting wafer which has islands of the opposite conductivity type, thestructure shown in FIG. 4 can be used. In FIG. 4 elements which are thesame as those shown in FIG. 3 are identified by the same referencecharacters. Thus, the polycrystalline silicon area C is surrounded bysilicon dioxide layer D which in this embodiment extends further outover the single crystal layers which are here both P-type and areindicated by reference characters I and P,

The image sensing writing diodes are formed by depositing a narrowerstrip 20a of N-type silicon by the above discussed sputtering techniqueabove the region P Similarly a narrower sputtered strip 211: of N-typesputtered silicon is first deposited above the single crystal area P,. Asecond layer 210 of P-type sputtered silicon is then deposited abovethis to form the read junctions between layers Zia and 21b. Thesenarrower layers 20a, 21a and 211) are formed in and surrounded by adielectric insulating layer D which is first deposited on the singlecrystal layers and is then etched to accommodate the sputtered depositsa, 21a and 21b. The transparent conductors T are then deposited as inThe FIG. 3 embodiment in a manner well known in the art.

The arrangement of FIG. 4 shows how, by the use of the silica layer D,it is possible to reduce the size of the write junction W and the readjunction R so that the capacitance and dark current can be reduced.Strictly speaking, the circuit which represents the structure shown inFIG 4 is not the same as that shown in FIG. 2. An individual element ofthe circuit of FIG. 2 (which represents the structure shown in FIG. 3)is shown in FIG. 5 In Fig. 5 it will be noted that the read diode R isconnected in series with the write diode W between conductors 11 and 14.On the other hand, in FIG. 6 there is shown an individual element of thestructure of FIG. 4. Here it will be noted that between conductors 11and 14 there is connected in series not only the read diode R, and thewrite diode W but also the excess diode X formed by the junction betweenlayer I and layer 21a. This excess diode X of FIG. 6 is biased in theforward configuration and hence does not change the operation of thedevice.

The devices of FIGS. 3 and 4 as described above will, on interrogationof a particular R diode by the scanning spot, give a signal which isdependent upon the light falling upon the corresponding W diode at thattime. Any change in the illumina tion falling on the W diode betweensuccessive scans will be without influence. For many purposes, this isundesirable and it is necessary to integrate the amount of light fallingon an individual W diode between successive scans and then, during thenext scan, read out this information. This can be done with the additionof a capacitor as shown in the schematic circuit diagram of FIG. 7 andthe corresponding structure of FIG. 8. The circuit of FIG. 7 is of thetype shown in FIG. 6 and related structures an parts which have beenpreviously discussed are identified by previously used referencecharacters. It will be noted in FIG. 7 that each of the write diodes hasan integrating capacitor in parallel with it. Thus, the capacitor 3B isconnected in parallel with diode W the capacitor 32 is connected inparallel with diode W and the capacitor 33 is connected in parallel withdiode W One device embodying the circuit of FIG. 7 is shown in FIG. 8.This structure of FIG. 8 also shows how an unmodified dielectricisolation semiconductor wafer can be used to fabricate these linearsources. The details of construction shown in FIG. 8 will be describedbelow.

Consider now the operation of the circuit shown in FIG. 7. Assume thatat the beginning of the first scan all W diodes are dark. There is nocharge on the capacitors 31, 32, or 33 because the R diodes arebackbiased. As the scan begins, each R diode conducts and charges thecorresponding capacitor. Now, assume the image to fall on the associatedW diode. This will result in some of the charge on the capacitor beingdissipated. The amount dissipated will depend on the amount of lightfalling on W since this determines the variation in its resistance. Atthe next scan, the capacitor is recharged and the amount of chargingcurrent which will flow will depend upon how much charge was dissipatedfrom the capacitor since the previous scan. This, in turn, depends uponthe total amount of light which fell on W between successive scans. Itmight at first appear that this scheme required that the W diodes bedark when the R diodes are being scanned so that the capacitor can befully charged. This is not so. If a particular W diode happens to beilluminated during the charging cycle, an increased amount of currentwill indeed flow during the charging cycle. This will be sensed as anincreased voltage across the load resistor during the first chargingcycle and, since the capacitor was not fully charged at that time, as anincreased voltage during the next charging cycle. This is not adisastrous circum stance for two reasons. First, the illumination of aparticular diode affects the charging current in the manner justdescribed for a period of time equal to (llL/s) T, where T is the timerequired to scan the entire array, L is the length of the array, and sis the distance between the centers of adjacent elements. Since L islarge and s is small (typical values are 9 inches and 2X10 inches,respectively), the influence will be small. Second, the effect of suchillumination would be to give an indication, for two successive scans,that the particular element was illuminated. But this is exactly whatthe situation at that particular element was, and it is this informationthat is to be extracted during the readout. To summarize, the effectwould be to reduce the resolution, in time, by an amount which is toosmall to be important.

As noted above, the circuit of FIG. 7 is embodied in the device shown inFIG. 8. This structure also shows how an unmodified dielectric isolationwafer prepared in a manner taught by US. Pat. No. 3,320,485 issued to J.L. Buie on May 16, I967 can be used to fabricate these linear sensors.In FIG. 8 like reference characters are again used to refer to elementscorresponding to those which have already been described. Thus, apolycrystalline substrate C has formed therein dielectric isolationlayer D. Within these isolated areas the single crystal P-typesemiconductor is converted to a P+ region as at 41 and 42 respectivelyby conventional diffusion techniques. This diffusion leaves theundiffused single crystal P-type silicon areas 43 and 44 respectivelywithin the difiused P+ areas and adjacent to the top surface of thewafer. An insulating silicon dioxide layer is then deposited over thistop surface to form the isolation patterns D. Before the isolation layerD is deposited, a metal contact strip 45 is deposited above the region41 and a second metal contact strip 46 is deposited above the region 42.The silicon dioxide is then deposited over these and a portion of it isthen etched away to permit the sputter deposition of a strip 47 ofN-type silicon forming at the interface between it and the P-region 43the series of write junctions W. Additionally, a similar strip is etchedaway above the region 44 and an N-type layer of silicon is first sputterdeposited at 48. Thereafter, a P-type silicon layer is deposited aboveit at 49 to form between the layers 48 and 49 the read junctions R. Thetransparent conductive strips are next evaporated by first applying acomplete layer or thin film of gold or tin oxide and then etching outthe lines separating the conductive transparent strips T which resultfrom this step.

The write junction W is indicated between region 43 and strip 47 by thearrowhead line whereas the read junction is similarly indicated betweenstrips 48 and 49. Of course the X- junction is formed between regions 44and 48 but is not indicated in FIG. 8 for clarity. The capacitor 31 isformed between the lower surface of the transparent conducting strip Twhich serves as an upper capacitor plate and the junction between region43 and the silicon dioxide layer above it. The region 43 is of courseconductive silicon and its top surface serves as the other plate of thecapacitor. The dielectric of the capacitor is indicated in FIG. 8 by thethe underlined reference character 31 and comprises the portion of thesilicon dioxide bounded by the upper surface of region 43, the lowersurface of conductive strip T and by the strip 47 and the edge of thedielectric isolation area D. This capacitor serves the function of thecapacitor 31 in FIG. 7. The operation of this device has been discussedabove in connection with FIG. 7.

The circuit shown in FIG. 9 is similar to that shown in FIG. 7 exceptthat the functions of charging and readout are separated. The structurecorresponding to this circuit is shown in FIG. 10. Again in both FIGuresreference characters which have been previously used for identical itemsare repeated. The image source is omitted in FIG. 9 for clarity ofillustration but would be the same as in all other Figures. The scansource shows two scanning beams one slightly leading the other for areason to be described below.

In this scheme each capacitor is charged through diode CD after it hasbeen interrogated by the scanning spot through diode R by the secondbeam from the same scanner. The unidentified diode associated with diodeCD is nonfunctional and arises from the method chosen to build thedevice as shown in FIG. 10. In the circuit as configured in FIG. 9 noload resistor is necessary since a voltage output is being takendirectly across the diode R,. If a load resistor is included in thecharging circuit of FIG. 9, there are then available two places toextract information as to the amount of light which fell on the W diodessince the previous scan. It will be noted that the conductor 14 leads toterminal 13 which is a common between the negative input tenninal l2 andthe negative output terminal 15 since positive output terminal 16 isdirectly connected to 13.

In FIG. the corresponding structure is shown comprising the substrate Cin which dielectric isolation regions are formed by barriers D and inwhich diffusion layers are then formed as in FIG. 8. It will be notedhowever that a third dielectric isolation region is used in which adiode CD is formed by depositing sputtered layers 50 and 51 above thediffusion area and providing the metallization conductive strip 52.

While a specific preferred embodiment of the invention has beendescribed by way of illustration only it will be understood that theinvention is capable of many other specific embodiments andmodifications and is defined solely by the following claims.

What is claimed is:

l. A linear solid state photo sensor device comprising:

a. a semiconductor substrate having at least two elongated parallelregions each having a predetermined conductivity of a type opposite fromthe other:

b. means interposed between said regions to isolate them from each otherelectrically;

c. a semiconductor layer above each of said regions, each of said layersbeing of a conductivity type opposite to that of its associated regionto form a photosensitive rectifying junction therewith;

d. means interposed between said layers to isolate them from each otherelectrically;

e. a plurality of transparent conductive strips parallel to each otherand perpendicular to said elongated regions, each strip connecting thepair of rectifying junctions under it in electrical series circuitrelationship in the same direction;

f. electrically conductive contact means on the lower surface of each ofsaid regions to connect said plurality of pairs of series connectedjunctions in parallel circuit relationship:

g. voltage means connected across said parallel circuit to apply reversebias on each pair of said rectifying junctions; and

h. optical scanning means for scanning the portions of said transparentconducting strips overlying one of the rectifying junctions of each saidpairs.

2. Apparatus as in claim 1 wherein an integrating capacitor is formed inparallel circuit relationship with the other one of the rectifyingjunctions of each said pair of junctions 3. In combination comprising:

a plurality of pairs of photosensitive diodes positioned adjacent toeach other in linear sequential relationship to form an elongated imagesensing element, the diodes of each pair being connected in an electricseries circuit relationship and all of the pairs of diodes beingconnected in electric parallel circuit relationship;

means for applying an input voltage across said parallel circuit;

the first diode in each of said pairs being positioned immediatelyadjacent to and coaligned with a corresponding diode in a succeedingadjacent one of said pairs so as to receive a linear segment of anoptical image falling thereon, said first diodes each being reversebiased;

a second diode in each of said pairs being positioned immediatelyadjacent to a second diode in another of said pairs to form a linearswitching segment, said second diodes each being reverse biased; and

an optical scanning means for scanning said linear switching segment toread out from each of said pairs of diodes the intensity of light insaid ima e. 4. The combination set fort in claim 14 wherein said diodescomprise an integrated circuit formed in a semiconductor substrate, saidintegrated circuit having at least 5,000 diodes per linear inch of saidsensing element.

5. The combination set forth in claim 3 wherein each of said firstdiodes has an integrating capacitor connected in parallel therewith.

Column Column Column Column Column Column Column Column (SEAL) PatentNo.

Inventor(s) Attest EDWARD M.FLETCHER, JR. Attesting Officer UNITEDSTATES PATENT OFFICE CERTIFICATE OF CORRECTION 3,609,375 Dated September28, 1971 Murray Bloom It is certified that error appears in theabove-identified patent and that said Letters Patent are herebycorrected as shown below:

line 6 after "Pat." insert specificationline 8 delete "449,885" andsubstitute -449,855

line 38 delete "the" second occurrence and substitute theyline 70 delete"21a" and substitute -2lb line 2 delete "The" and substitute -the-- line34 delete "an" and substitute -and-- u line 1 delete 2X10 and substitute-2Xl0 line 33, in claim 4 delete "l4" and substitute -3 Signed andsealed this 28th day of March 1972.

ROBERT GOTTSCHALK Commissioner of Patents RM PO-105O (10-69) USCOMM-DC60376-P69 e u 5. GOVERNMENT PRINTING OFFICE I969 O36633|

2. Apparatus as in claim 1 wherein an integrating capacitor is formed inparallel circuit relationship with the other one of the rectifyingjunctions of each said pair of junctions
 3. In combination comprising: aplurality of pairs of photosensitive diodes positioned adjacent to eachother in linear sequential relationship to form an elongated imagesensing element, the diodes of each pair being connected in an electricseries circuit relationship and all of the pairs of diodes beingconnected in electric parallel circuit relationship; means for applyingan input voltage across said parallel circuit; the first diode in eachof said pairs being positioned immediately adjacent to and coalignedwith a corresponding diode in a succeeding adjacent one of said pairs soas to receive a linear segment of an optical image falling thereon, saidfirst diodes each being reverse biased; a second diode in each of saidpairs being positioned immediately adjacent to a second diode in anotherof said pairs to form a linear switching segment, said second diodeseach being reverse biased; and an optical scanning means for scanningsaid linear switching segment to read out from each of said pairs ofdiodes the intensity of light in said image.
 4. The combination setforth in claim 14 wherein said diodes comprise an integrated circuitformed in a semiconductor substrate, said integrated circuit having atleast 5,000 diodes per linear inch of said sensing element.
 5. Thecombination set forth in claim 3 wherein each of said first diodes hasan integrating capacitor connected in parallel therewith.